In an attempt to further increase circuit density, three-dimensional (3D) ICs have been developed. For example, two dies are bonded together and electrical connections are formed between the two dies. The stacked dies are then bonded to a carrier substrate using wire bonds and conductive pads. In another example, a chip on chip on substrate (CoCoS) technique or a chip on wafer on substrate (CoWoS) technique is developed.
However, for example, in the CoWoS technique, while a plurality of chips are being bonded to a wafer, the wafer may exhibit a cracking issue along a direction parallel to the edges of the chips. The cracking issue may result from the bonding stress imposed on a relatively weaker crystal plane of the wafer.